Hi, I'm new to this board! This seems to be one of the very few resources about IGS PGM, so I hope to share some info!
Basically I want to do some conversions, but don't want to sacrifice existing (working) carts. I have little interest in a multi-cart, I just want the games that have no cartridge release. There is very little information about the internals of the PGM compared to MVS, so I decided to make a start with decoding some pinouts.
Attached is a schematic from my Knights of Valour 256-1 board (A-ROM, B-ROM and M-ROM), as I thought that would be easiest without the ASIC or any PALs.
I started this on an A4 sheet but ran out of space, that is why things are a bit tight. When I started with the M ROM I didn't realise it is used 8-bit wide (even though the Mame driver should've been a hint), that is why address lines are all off by one. They should start at A0 and not A-1, but that is what you get when you operate an 8/16 rom in byte mode.
The WE line of all the A and B ROMs should be BYTE mode as well, just set to 16-bit. I didn't spend too much time looking at the chip selection logic for them, so that may need some work as well.
For now I didn't label all networks, any signal A* should be A-ROM, B* should be B-ROM and M* should be M-ROM. The pinout of the cartridge looks a bit messy, I have no idea how much is my error, intentional obfuscation or manufacturing convenience...
There are probably plenty of errors as I did this while watching TV, and I'm sure my probe has slipped a few times as well. I plan to compare this against a Dragon World II after I've done the P and T board.
By the way, has anyone looked at BIOS calls, or any headers and entry points for the executable ROM? I planned to ask the authors of the Mame driver, but they seem to have left the scene and I don't want to bother them.
Update: Attached a WIP of the PROG board as well. This is for the 0257-1 board with P and T roms and the ASIC. All the ROM footprints seem to be in parallel for the P-ROMs, the smaller 27c040 footprints are for separate HI and LO ROMs. All the data and address lines are connected, just for different pinouts. All the P-ROM access seems to go through the ASIC, which I can't be arsed to trace today, and I don't know if I'll have time in the remainder of the year.