- Thread starter CoolFox
- Start date
plasticfactory
Grand Master
full send
skate323k137
Enlightened
The above discussed visible artifacts of the open areas of the multi layer circuit board are a good place to start, immediately evident from the solder masking.
XtraSmiley
Legendary
mypinballs
Professional
, boards will be available for people to build from scratch, or populated with just the ics to add.
Alright, we're at $1000. Coming down rather quickly. 
Still needs to be halfed once or twice more before I consider.
Besides, someone was joking about having stolen the gerber files but this is the most likely scenario. Cave designed and licensed someone to make this platform at some point (Taiwan?) and those files are now out there. It's a four layer pcb, I don't think someone could disassemble it and make, what looks like, a 1:1 copy otherwise.
Still needs to be halfed once or twice more before I consider.Besides, someone was joking about having stolen the gerber files but this is the most likely scenario. Cave designed and licensed someone to make this platform at some point (Taiwan?) and those files are now out there. It's a four layer pcb, I don't think someone could disassemble it and make, what looks like, a 1:1 copy otherwise.
Last edited:
You can take layers off of a PCB. Think about decapping chips as a comparison. It's just rarely worth the effort/price to do so. I'm not sure X-Ray works well on a 4-layer PCB, but I've seen folks do it on 2-layers.
I'd imagine a lack of SH-3's would be the real bottleneck here. Last time I went looking there were not many available on the market. Not in a commercial sense of "many" anyhow.
What kind of FPGA is on there? If that is not available you won't be able to upload the bitstream, either. Also I have no idea if that is encrypted/protected in any way.
Someone doing stuff like https://www.tindie.com/stores/bobsbits/ for Retro computers posted pictures, they sand off the soldermask, then make a high-res scan, then sand off that layer and make another scan. Though for most Retro hardware there are plenty of damaged PCBs, so nobody cares about a few being destroyed in the name of science. (And you can still reuse the chips to fix other machines.)
X-Ray is a good alternative, though out of reach of most hobbyists. There are companies providing this service, but they want $$$.
Someone doing stuff like https://www.tindie.com/stores/bobsbits/ for Retro computers posted pictures, they sand off the soldermask, then make a high-res scan, then sand off that layer and make another scan. Though for most Retro hardware there are plenty of damaged PCBs, so nobody cares about a few being destroyed in the name of science. (And you can still reuse the chips to fix other machines.)
X-Ray is a good alternative, though out of reach of most hobbyists. There are companies providing this service, but they want $$$.
Last edited:
Nice shop. I didn't know that one.
| To power the successors of Espgaluda, CAVE designed a new hardware platform based on the powerful Hitachi SH-3 processor. The graphics are handled by a dedicated FPGA and the protection resides in a CPLD. There are no more EPROM DIL sockets, instead all of the software is stored in FLASH. The PCB is equipped with an EEPROM which saves your high scores. This is a generic platform which can be reprogrammed by CAVE using JTAG technology. I.e. an Ibara may be converted to a Mushihimesama if desired However it looks as if U23 & U24 (Sound Data) are not a part of the JTAG chain and are most likely preprogrammed before mounting. | |
| PCB | CV1000-B |
| C126 (BATTERY) | CR 2450, Powers the RTC (Real Time Clock) U10. Look at the garden clock in Ibara. |
| U21 (AMPLIFIER) | LA 4708 |
U5 (CPU) | Hitachi SH-3 @ 133 MHz (7709S) |
| U22 (SOUND CHIP) | Yamaha YMZ770C-F |
| U23-U24 (FLASH) | MBM 29DL321, 32 MBit CMOS 3.0V, Sound data. |
| U6 (SDRAM) | MT46V16M16 – 4 MBit x 16 x 4 banks, RAM (256 MBit) |
| U7 (SDRAM) | MT46V16M16 – 4 MBit x 16 x 4 banks, RAM (256 MBit) |
| U1 (SDRAM) | MT48LC2M32 – 512K x 32 x 4 banks, (64 MBit) |
| U8 (FPGA) | Altera Cyclone EP1C12 FPGA |
| U13 (CPLD) | Altera EPM7032 (MAX 7000 Series), Most likely the protection chip. |
| U4 (FLASH) | 29LV160BB 16M-BIT CMOS 3.0, Boot device, FPGA bit file, main program code |
| U2 (FLASH) | K9F1G08U0M 128M x 8 Bit / 64M x 16 Bit NAND. Graphics data. |
| U27 (SUPERVISOR) | MAX 690S 3.0V Microprocessor Supervisory Circuit |
| U10 (RTC & EEPROM) | RTC 9701, Serial RTC Module with EEPROM 4 kbit (256x16 bit), controlled by U13 |
| U12 (RS-232 TRANCEIVER) | MAX 3244E RS-232 Tranceiver, only mounted when P5 is mounted |
| S3 (MICRO PUSH BUTTON) | Test switch, same as on the JAMMA connector |
| S1 (DIL SWITCH) | Half Pitch DIL Switch x 1, function unknown |
| S2 (DIL SWITCH) | Half Pitch DIL Switch x 4, SW1=Setup, other switches unknown |
| P2 (IDC CONNECTOR 20 PIN) | function unknown, P2 is not always mounted |
| P4 (IDC CONNECTOR 14 PIN) | JTAG connector |
| P8 (IDC CONNECTOR 10 PIN) | Advanced User Debugger |
| P3 (CONNECTOR) | Most likely an expansion port, P3 is not always mounted |
| P5 (CONNECTOR) | Most likely a serial connector. Only mounted on early Mushihimesama PCB's |
| P7 (CONNECTOR) | Network port pinout. Never seen mounted on any PCB. |
| D1-D6 (LED) | Status LED's. D6 lights up at power on then shuts off, D2 indicates coinage. |
Source: rtw, Ex-Cyber & Guru [R3]
The FPGA is obsolete as well: https://www.digikey.de/short/5b19dh4p
In short, I think it is more likely that someone will invest the time into a Mister (or Mister successor) core than making a reasonably priced clone of the PCB. You not only need to invest the time to make the PCB, but acquire a good amount of the required chips. Considering that many people will happily sell you re-labelled junk this will be expensive and time consuming.
In short, I think it is more likely that someone will invest the time into a Mister (or Mister successor) core than making a reasonably priced clone of the PCB. You not only need to invest the time to make the PCB, but acquire a good amount of the required chips. Considering that many people will happily sell you re-labelled junk this will be expensive and time consuming.
Yeah the fpga is old.. I read somewhere that a CORE for the SH-3 was under development but that's probably halted long ago.. :/
the SH-3 is still listed as ACTIVE, and its possible to order from the manufacturer.. (PLP mar 2025)
https://www.renesas.com/us/en/produ...e-family-mcus/sh7709s-32-bit-microcontrollers
mouser has it too.. but only on order, and 72pieces min
but I have no idea how one would go about changing to a never cyclone fpga.. the bitstream is embedded in the romfile.. and that probably takes some high level wizardry to adapt/read/whateveryoudowithit
the SH-3 is still listed as ACTIVE, and its possible to order from the manufacturer.. (PLP mar 2025)
https://www.renesas.com/us/en/produ...e-family-mcus/sh7709s-32-bit-microcontrollers
mouser has it too.. but only on order, and 72pieces min
but I have no idea how one would go about changing to a never cyclone fpga.. the bitstream is embedded in the romfile.. and that probably takes some high level wizardry to adapt/read/whateveryoudowithit
Last edited:
These things always depend on someone to sit down and say "I want this to happen". I have no idea how different the SH-3 is, but there is a Saturn core making good progress. The FPGA seems to work mostly as a Blitter, so reimplementing this shouldn't be rocket surgery.
The tricky bit will be to match the timing, a lot of the "experience" of the original board is the slow-down from overloading the Blitter or the CPU. One of the blogs had a survey where this has an impact.
Edit: CPS-3 is SH-3 as well, isn't it?
Edit:
You would need to recover the netlist from the bitstream, then re-fit it for a new FPGA. That will be hindered by undocumented internals and trade secrets, so you'll need to reverse-engineer the FPGA first. And the timing constraints on the new FPGA will be different as well, so you'll need to understand the netlist to redesign it for the new FPGA.
Last edited:
I spent a lot of time looking at the timing for emulation purposes, see https://buffis.com/research/cv1000-blitter-research/ and some later posts in that blog.
For actual blitter ops and vram behavior, you can look at the mame source.
No way Mister can handle it btw
Someone already started to port mister to a larger FPGA, it is only a matter of time for the DE-10 to be replaced with something more powerful.
