Second Test with VHDL, I am using "
Intel® Quartus® II Web Edition Design Software Version 13.0sp1 for Windows". which is the last version supporting the MAX7000 devices (which are similar to the ATF150x devices):
Quartus supports VHDL, Verilog and a schematic editor. I used Pascal for a long time so VHDL looked most appealing to me. I expect the synthesis/fitting back-end is the same for all three options, so it depends only on someone's preference what to use.
Unfortunately I can't recommend the Quartus -> pof -> jed pipeline. I had it twice now where I got non-working chips: Once with a Verilog project for a someone, which was split into a few modules. This produced a chip where not all features worked correctly. Mysteriously these features worked when I put them as test circuit on unused pins of the top design, and when I inlined all separate modules into the top design.
The second was with my own VHDL project, with only a single top level file. It worked initially, then stopped working when I removed an unnecessary part of the design.
In both cases the RTL schematic looked perfectly fine, I didn't get any errors during synthesis or conversion.
What I ended up doing is use
GHDL to convert my VHDL to Verilog, then
JsonToCupl to use
Yosys for synthesis and Cupl for fitting. Also I found
fuseconv to convert the jed to svf, which is easier then running ATMISP all the time. The differences between an svf file produced by fuseconv and ATMISP seem to be cosmetic.
I put everything into batch files so I can quickly run it from Visual Studio Code.
Of course, there are alternatives: The commercial version of Yosys contains a VHDL compiler (if you want to use VHDL), also the fitter included in ProChip Designer can use EDIF output from Yosys directly (though I didn't find a working link last time I looked, and I don't know if the fitter works without a license).
