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Ape Cosplay

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Hello,

The CPS1 from Capcom, as we all know, was a great system, host of many glorious games from the late 80s/early 90s such as Ghouls'n Ghosts, Final Fight... And Street Fighter II of course!

It's also infamous for its custom chips having a very high failure rate, with no replacement as of today, turning valuable hardware in paperweights...

In late 2019 @WydD (Loic Petit) took the challenge to fully reverse CPS2, boards and custom chips, including the two also used on CPS1. And he did succeed, what an incredible effort towards preservation!

It surely helped develop the MisterFPGA cores, but nothing came out of it that could help revive boards with dead custom chips.

Some argued it would be difficult to find a FPGA that could fit inside the original footprint (QFP160), but as we know, necessity is the mother of inventivity, proved by @caius and others, designing small adapter boards, sometimes with mezzanine connectors.

The real work was in fact converting the 83 page schematics provided by @WydD to Verilog (or any other HDL langage used by modern FPGA engineering tools).

And so it begins...

1736451899862.png


I'm only getting started, fully realising the mountain of work before me, but hey, you have to start somewhere.

By making it public so early I hope to find the motivation to give you guys regular updates, It may take 6 months or a year, who knows...

Wish me luck!
 
Loving this! Really interested to see where the road leads, so much interest and innovation in this platform.
 
Absolutely fantastic. Look forward to hearing those page numbers getting knocked down!
 
A question for @WydD if he reads me.

There a discrepancy on p5 between the schematics and the annoted equations, who's right?

1736466953725.png


[EDIT]
The bit maskings seem to indicate the schematics are correct wrong.
 
Last edited:
The schematics have been fixed. The comment and binary pattern was right, I have no idea how I made that mistake, that's weird.
I took the opportunity to finally fix the CI pipeline so now it's will immediately publish new svg/pdfs whenever I need to change something.

@MickyMac It's not that simple. Jotego's core fully reimplement the behaviour of the whole hardware not just the dl-0311. So you cant directly extract a DL-0311 verilog as it's bits and pieces from everywhere.

By the way I realize I havent spoken about the project itself: this is cool! And I will follow the project obviously.
 
That is some undertaking. I know nothing about mister development but everyone says the mister cores are 1-to-1 with original hardware so if that's the case would the fpga implementation of CPS-A-01 not already be completed by jotego and in the source? https://github.com/jotego/jtcores/tree/master/cores/cps1
Nah. Unless a chip had been perfectly decapped and documented perfectly a Fpga can only be as perfect as its documentation and then a programmer.
Is Mister impressive? Yes. Is it anywhere near perfect for most cores?
No.
 
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