What's new
By:

MV1AX. Z80->68k comm issue (ack)

Checked connection between main- and slot pcbs. Found some missing connections.

Edit: fixed these but no luck chuck. Exactly the same behaviour.

Was it really bad connections or did I just do something wrong when I measured?


Am I going insane?
 
Last edited:
kissedin said:
Checked connection between main- and slot pcbs. Found some missing connections.

Edit: fixed these but no luck chuck. Exactly the same behaviour.

Was it really bad connections or did I just do something wrong when I measured?


Am I going insane?
Click to expand...

Did you try swapping the LS32?

I got errors randomly popping up, and now it's fixed on 001100 after swapping it.

Also i got misslead due to z80 RAM not well inserted in the socket.

I know it's not a very clever way to solve the issue but we struggle the same sh**.

At least one of us might survive this madness lol
 
Finally this little quest seems to have come to an end. Today I got sound on KOF'99, RBFF and metal slug x.

I have fixed a couple of mvs. But mostly easy stuff like ram errors. I have no deep insight in the architecture. But here is what I did ...

I compared how the prog cart pins and pcm chip behaved on Karnovs Revenge (which has worked all the time) and KOF'99. Noticed that alot of pins were dead on KOF'99 - but pulsing on KR. Almost like the sound driver wasn't running at all. Maybe the switch to m1 was never done?

So I googled (which I usually do and don't end up writing long monologues on forums like this) and found this beautiful little thread:
https://www.neo-geo.com/forums/index.php?threads/z80-error-mvs-mv-1fzs.259037/

It mentions chip enable on pin CHA 49B. I probed it with KOF'99 running. It was stuck but i can't remember if it was High or Low.

I traced this pin back to the mother board. It lead to a LS32 which is a 4 OR-gates.

Pin out:
10 OR 9 = PIN 8 (CHA 49B)
Pin 10 is connected to output on pin 6 (pin 6=pin 10).
Pin 9 = ... never traced.

5 OR 4 = pin 6

Pin 4 is connected to NEO-I0 pin 19 (ORI0) (aka SDROM?)
Pin 5 is connected to AS04N @ U9 pin 8.

A lot of vias and traces across the board. After this exercise I wanted to study the signal.

I started at pin 49B but now it was pulsing. And I heard music.

When reading on NEO-I0 on neo-dev it says "SM1CS(ORO0): SM1 ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)"

I don't fully understand this text. But it seems that the ORO0 (output?) is a result of ORI0 and ORI1 (inputs?).

So what was the final fix? With no fault present it's hard for me to to find a better conclusion than a bad vias somewhere on the chip enable. This caused the logic to malfunction.

Signal got through on smaller carts like PB and KR but didn't manage on bigger and more power consuming games.

I almost wish the problem comes back. Almost.

Thank you all for you help. And a special thanks to ack for developing and supporting smkdan's diagrom.
 
Last edited:
You must log in or register to reply here.
Back
Top