Neo Geo MVS. Bought as non working. Seller said it randomly booted with Unibios IF a cart was inserted.
Board looked nice and clean. Someone had obviously tried to fix it. New backup-rams, U4990-chip had shiny solder. All hot glue (which is from factory to avoid vibration) was removed. New capacitors.
Powered on with no cart and stock bios: Click of death.
Powered on with cart and stock bios: Green screen, then a “calendar error”
Powered on with no cart and unibios: Click of death.
Powered on with cart and unibios: "Hardware test failed: the BIOS". Pressed A – and games ran perfect.
Googled and found three threads, which all described the same problem as I had:
https://www.neo-geo.com/forums/index.php?threads/calendar-error-unibios.143524/
https://forums.arcade-museum.com/threads/neo-geo-mvs-address-bus-no-signal.299161/
https://www.neo-geo.com/forums/inde...bled-suspect-address-decoding-failure.259413/
And of course all threads just died out without any solution, conclusion or anything. User channelmaniac advised to check back up-circuit in the thread on arcade-museum. So I decided to start there.
Scoped the clock-signal; ran at perfect speed: 32.768 kHz. Traces tested ok. Decided to take a look on what the enable lines (WE, CE, OE) were doing.
The WE lines to backup ram is supposed to be handled by a HC32-chip (AND-gates). But to my surprise there was a LS32-chip instead. I tried to read upon this and it seems that LS have more liberal voltage thresholds (LS TTL 0,8/2,4V vs. HC CMOS 0,3/3,6V) but is slower. Maybe the LS32 was deliberately put there as an attempt from previous repair-tech?
I put everything aside and replaced the LS32 with a new HC32. Powered on. Enable lines looked ok. Didn’t see the text “calendar error” when using stock bios and cart after this. Instead I got stuck on a green screen (which is a symptom of calendar error, but I ruled out the back-up circuit anyway).
Shifted focus towards the weird boot behaviour. /OE on main bios read H. Maybe some corrupt signal made the system believe that a cart was plugged in? This signal is called ROMOE.
ROMOE-signal comes from an AND-gate from chip U15, a 74LS08:
NEO C1 pin 91 “ROMOEL” -> U15 pin 13
NEO C1 pin 5 “ROMOEU” -> U15 pin 12
U15 pin 11 “ROMOE” -> slot connector 33B -> P1 ROM pin 13 “/OE” (on PROG-Board).
Oscilloscope showed pulsing behaviour on all lines (no cart inserted). (Edit: now I know that all signals above should promptly go High when booting with no cart. Pin 11 "ROMOE" shall start pulsing after the green screen in the boot process)
I desoldered a jumper to p1rom pin 13 on a scrap cart and tried to boot with it: click of death even with a cart. Of course… Because there is no PROM to read from at all.
Read further on neo dev. There is also a signal called SROMOE - system rom output enable or just "/OE on bios". It is generated by an AND-gate but from SROMOEL and SROMOEU.
NEO C1 pin 96 “SROMOEL” -> NEO E0 pin 60 “ANI1”
NEO C1 pin 12 “SROMOEU” -> NEO E0 pin 60 “ANI0”
NEO E0 pin 59 “AND0” -> SP1 ROM pin 20 “/OE”.
Both ANI1 and ANI0 were H. And therefore the AND0 was H. So obviously the system didn’t enable the main bios. Hence the click of death.
Why didn't ANI0 or ANI1 go low? A faulty Neo-E0? Or a faulty Neo-C1? Or corrupt instructions? I scoped Neo-E0 and found that the VEC signal was pulsing but had a DC offset of 2,64V. This was interesting. Reading on neo dev: A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a P ROM access. - https://wiki.neogeodev.org/index.php?title=NEO-E0
(“A22Z” and “A23Z” might be a typo and are meant to be “A22I” and “A23I”. I also believe that the pinout for MV2F and AES is the same for MV1FZS (I haven't checked the pins that handle memory card for obvious reasons).)
Anyway: when VEC-signal is H it toggle input from A22 and A23 to A22I and A23I (whose outputs goes to NEO C1 pin 25 and pin 26).
So: If VEC is corrupt (stuck high or floating) NEO C1 which handle output enable to the main bios, malfunctions.
Tracing the VEC-signal:
Neo E0 Pin 62 “VEC” <- U7 74HC259 pin 15 “Q1”
Scoping output pin Q1 on chip U7: Some Q-lines (output) looked good and some had the dc-offset. Data line looked good. So did the VCC, GND and address lines.
Replaced U7 with a new one and powered on. Same ol’ click of death.
Noticed that the bios socket was empty. Put in stock-bios. And ... booted to cross hatch! Tried some games, diagrom with z80-cart (all test pass) and applied new hot glue. Had a soda.
Board looked nice and clean. Someone had obviously tried to fix it. New backup-rams, U4990-chip had shiny solder. All hot glue (which is from factory to avoid vibration) was removed. New capacitors.
Powered on with no cart and stock bios: Click of death.
Powered on with cart and stock bios: Green screen, then a “calendar error”
Powered on with no cart and unibios: Click of death.
Powered on with cart and unibios: "Hardware test failed: the BIOS". Pressed A – and games ran perfect.
Googled and found three threads, which all described the same problem as I had:
https://www.neo-geo.com/forums/index.php?threads/calendar-error-unibios.143524/
https://forums.arcade-museum.com/threads/neo-geo-mvs-address-bus-no-signal.299161/
https://www.neo-geo.com/forums/inde...bled-suspect-address-decoding-failure.259413/
And of course all threads just died out without any solution, conclusion or anything. User channelmaniac advised to check back up-circuit in the thread on arcade-museum. So I decided to start there.
Scoped the clock-signal; ran at perfect speed: 32.768 kHz. Traces tested ok. Decided to take a look on what the enable lines (WE, CE, OE) were doing.
The WE lines to backup ram is supposed to be handled by a HC32-chip (AND-gates). But to my surprise there was a LS32-chip instead. I tried to read upon this and it seems that LS have more liberal voltage thresholds (LS TTL 0,8/2,4V vs. HC CMOS 0,3/3,6V) but is slower. Maybe the LS32 was deliberately put there as an attempt from previous repair-tech?
I put everything aside and replaced the LS32 with a new HC32. Powered on. Enable lines looked ok. Didn’t see the text “calendar error” when using stock bios and cart after this. Instead I got stuck on a green screen (which is a symptom of calendar error, but I ruled out the back-up circuit anyway).
Shifted focus towards the weird boot behaviour. /OE on main bios read H. Maybe some corrupt signal made the system believe that a cart was plugged in? This signal is called ROMOE.
ROMOE-signal comes from an AND-gate from chip U15, a 74LS08:
NEO C1 pin 91 “ROMOEL” -> U15 pin 13
NEO C1 pin 5 “ROMOEU” -> U15 pin 12
U15 pin 11 “ROMOE” -> slot connector 33B -> P1 ROM pin 13 “/OE” (on PROG-Board).
Oscilloscope showed pulsing behaviour on all lines (no cart inserted). (Edit: now I know that all signals above should promptly go High when booting with no cart. Pin 11 "ROMOE" shall start pulsing after the green screen in the boot process)
I desoldered a jumper to p1rom pin 13 on a scrap cart and tried to boot with it: click of death even with a cart. Of course… Because there is no PROM to read from at all.
Read further on neo dev. There is also a signal called SROMOE - system rom output enable or just "/OE on bios". It is generated by an AND-gate but from SROMOEL and SROMOEU.
NEO C1 pin 96 “SROMOEL” -> NEO E0 pin 60 “ANI1”
NEO C1 pin 12 “SROMOEU” -> NEO E0 pin 60 “ANI0”
NEO E0 pin 59 “AND0” -> SP1 ROM pin 20 “/OE”.
Both ANI1 and ANI0 were H. And therefore the AND0 was H. So obviously the system didn’t enable the main bios. Hence the click of death.
Why didn't ANI0 or ANI1 go low? A faulty Neo-E0? Or a faulty Neo-C1? Or corrupt instructions? I scoped Neo-E0 and found that the VEC signal was pulsing but had a DC offset of 2,64V. This was interesting. Reading on neo dev: A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a P ROM access. - https://wiki.neogeodev.org/index.php?title=NEO-E0
(“A22Z” and “A23Z” might be a typo and are meant to be “A22I” and “A23I”. I also believe that the pinout for MV2F and AES is the same for MV1FZS (I haven't checked the pins that handle memory card for obvious reasons).)
Anyway: when VEC-signal is H it toggle input from A22 and A23 to A22I and A23I (whose outputs goes to NEO C1 pin 25 and pin 26).
So: If VEC is corrupt (stuck high or floating) NEO C1 which handle output enable to the main bios, malfunctions.
Tracing the VEC-signal:
Neo E0 Pin 62 “VEC” <- U7 74HC259 pin 15 “Q1”
Scoping output pin Q1 on chip U7: Some Q-lines (output) looked good and some had the dc-offset. Data line looked good. So did the VCC, GND and address lines.
Replaced U7 with a new one and powered on. Same ol’ click of death.
Noticed that the bios socket was empty. Put in stock-bios. And ... booted to cross hatch! Tried some games, diagrom with z80-cart (all test pass) and applied new hot glue. Had a soda.
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