Reproducing the one and only custom chip on Capcom's CPS1 A-boards, aka CPS-A-01 / DL-0311

[Ape Cosplay]

Hello,

The CPS1 from Capcom, as we all know, was a great system, host of many glorious games from the late 80s/early 90s such as Ghouls'n Ghosts, Final Fight... And Street Fighter II of course!

It's also infamous for its custom chips having a very high failure rate, with no replacement as of today, turning valuable hardware in paperweights...

In late 2019 @WydD (Loic Petit) took the challenge to fully reverse CPS2, boards and custom chips, including the two also used on CPS1. And he did succeed, what an incredible effort towards preservation!

It surely helped develop the MisterFPGA cores, but nothing came out of it that could help revive boards with dead custom chips.

Some argued it would be difficult to find a FPGA that could fit inside the original footprint (QFP160), but as we know, necessity is the mother of inventivity, proved by @caius and others, designing small adapter boards, sometimes with mezzanine connectors.

The real work was in fact converting the 83 page schematics provided by @WydD to Verilog (or any other HDL langage used by modern FPGA engineering tools).

And so it begins...

I'm only getting started, fully realising the mountain of work before me, but hey, you have to start somewhere.

By making it public so early I hope to find the motivation to give you guys regular updates, It may take 6 months or a year, who knows...

Wish me luck!

 

[hatmoose]

Loving this! Really interested to see where the road leads, so much interest and innovation in this platform.

 

[ForestOfDreams]

Well I fully encourage this effort.

 

[rewrite]

Absolutely fantastic. Look forward to hearing those page numbers getting knocked down!

 

[ShootTheCore]

Excellent! Very excited to see the end result one day, and it's reassuring that this reproduction is being tackled.

 

[Ape Cosplay]

A question for @WydD if he reads me.

There a discrepancy on p5 between the schematics and the annoted equations, who's right?

[EDIT]
The bit maskings seem to indicate the schematics are correct wrong.

 

[WydD]

Looking at the die it seems that the schematics are wrong https://petitl.fr/cps2/DL-0311/die/#x=16005&y=8351&z=7 (click on the red dots in the cell to display the line and the label).

Afaics
~LINE4 needs to be replaced by ~LINE3
~LINE5 needs to be replaced by ~LINE4

I'll double check and fix it this evening.

 

[MickyMac]

That is some undertaking. I know nothing about mister development but everyone says the mister cores are 1-to-1 with original hardware so if that's the case would the fpga implementation of CPS-A-01 not already be completed by jotego and in the source? https://github.com/jotego/jtcores/tree/master/cores/cps1

 

[Mrhide]

click on the red dots in the cell to display the line and the label

holy crap!

 

[WydD]

The schematics have been fixed. The comment and binary pattern was right, I have no idea how I made that mistake, that's weird.
I took the opportunity to finally fix the CI pipeline so now it's will immediately publish new svg/pdfs whenever I need to change something.

@MickyMac It's not that simple. Jotego's core fully reimplement the behaviour of the whole hardware not just the dl-0311. So you cant directly extract a DL-0311 verilog as it's bits and pieces from everywhere.

By the way I realize I havent spoken about the project itself: this is cool! And I will follow the project obviously.

 

[Ape Cosplay]

Thanks for taking the time to check.

[EDIT]

Looking at the die it seems that the schematics are wrong https://petitl.fr/cps2/DL-0311/die/#x=16005&y=8351&z=7 (click on the red dots in the cell to display the line and the label).

OK, a little too obscure for me right now.

 

[Hieroneus]

I love it, thanks!

 

[ForestOfDreams]

That is some undertaking. I know nothing about mister development but everyone says the mister cores are 1-to-1 with original hardware so if that's the case would the fpga implementation of CPS-A-01 not already be completed by jotego and in the source? https://github.com/jotego/jtcores/tree/master/cores/cps1

Nah. Unless a chip had been perfectly decapped and documented perfectly a Fpga can only be as perfect as its documentation and then a programmer.
Is Mister impressive? Yes. Is it anywhere near perfect for most cores?
No.

 

[Ape Cosplay]

Hey guys,

I'm only down 6/83 pages...
I let you guys forecast a date for the 83/83 goal.

 

[Ape Cosplay]

It took a while I know but here's a pretty big update.

@WydD has been kind enough to generate the complete Verilog from the KiCad schematics using this tool:
https://github.com/galacticstudios/KiCadVerilog/

Then he also pointed the fact that Jotego built a cell library for those Ricoh chips:
https://gitlab.com/jotego/cps2-reverse/-/blob/master/verilog/hdl/A5C-cells.v

Upon first compilation I got this:

Turned out some cells used by Loic were missing from Jotego's library, namely L4LH, M175C, M175CL, AOI24, OAI22, MUX24GH, M175CLH, AOI32, HA1, FA1, FA2, MUX42H, SSR256_10 and SSR256_16.
I created them all and compiled again...

Got many, many more errors and warnings

The reason for that is signal order in Loic's modules is different from Jotego's ones.

Below an example:

Loic

- pin 1 = CLK
- pin 2 = D
- pin 3 = !Q
- pin 4 = R
- pin 5 = Q

Jotego
module DFFCOR( // ref: DFFCOR
input clk, // pin: 1
input d, // pin: 2
input i4, // pin: 4
output reg q, // pin: 3
output reg q_n // pin: 5
);

So either we find a way to automatically fix that or I need to edit all the modules from Jotego's libray (a lot of them...).

 

[ForestOfDreams]

I have a handful of parts boards I could resurrect if this becomes a thing. Excellent progress.

 

[Ape Cosplay]

It compiles without error! But still a significant number of warnings (down from several thousands at some point, now most are "normal" actually).

And I know there are still things not right, hopefully @WydD can help tackle the last issues.

 

[Ape Cosplay]

For those curious about the "normal" warnings, here's an example of a gate with tri-state outputs where hi-impedance is never used (!E input hardwired to ground):

Quartus throws a warning for EACH output: