Reproducing the one and only custom chip on Capcom's CPS1 A-boards, aka CPS-A-01 / DL-0311

[Triple3fast]

Thank you for doing this. We all appreciate you for this!

 

[Hieroneus]

Hi, have you got any solution? Thanks!

 

[Ape Cosplay]

Nope... none.

 

[RepairGuy95]

@WydD help save some boards.

 

[Hieroneus]

Its the A Board, A-01 i think

 

[Kaelan]

Any update on this? CPS1 boards have been dropping like flies lately, this could be a real game changer in keeping them alive.

 

[atrac17]

@WydD, I wanted to thank you here, because none of what I just released would have been possible without your work.

I've released a beta of CPS-1 for MiSTerFPGA and the Analogue Pocket, and its CPS-A and CPS-B come straight from your DL-0311 and DL-0921 traces. I retraced both chips against the die photographs, turned them into gate-level netlists, and simulated them together on a model of the 89626A-4 DASH A-board and 91634B-2 B-board. The first frames out of them were a black screen with a few blocks in two or three colors. These are the corrections it took to get both chips drawing real game frames:

DL-0311 (CPS-A)

• A bus request clock pin wired to the reset rail
• Scroll decoders with their spare inputs tied low, so they never fired
• Scroll drivers enabled at the wrong time and fighting the sprite driver
• Video RAM timing inverters wired in reverse order
• A sprite address gate that read sprite entries from the wrong area
• The frame buffer's X and Y write buses crossed
• A palette bus run to the wrong bus
• A frame buffer counter clocked on the wrong phase
• The scroll pads in reversed order
• Gates whose type or wiring only the die could settle, among them ORs that are NORs, a toggle clocked from the wrong phase, and swapped inputs on complex gates

DL-0921 (CPS-B)

• A debug bus drawn in place of the test data bus
• Duplicate address labels shorting address bits together
• The palette copy pads
• Six layer-order flip-flops with their clock and clear swapped
• Graphics load strobes on the wrong half of the clock
• Scroll 1 and scroll 3 outputs latched on the wrong strobes
• Swapped fine-scroll delay paths
• A scroll 3 counter loading six pixels late
• The key registry's address order
• The bit order into the shift registers
• The clock of the blanking and sync registers
• A missing cell, without which the scroll 2 palette never updated

I have a PR coming for your repo with these corrections if you want it. For the DL-0921, John McMaster gave me access to his unpublished die photographs, and I checked the corrections on that chip against them. He has also authorized releasing them publicly in full, so they'll be out alongside the netlists.

Thanks again, Loic. Your reverse engineering work on CPS2 is the foundation all of this was built on. There's some more information available here: https://www.patreon.com/atrac17/posts/coin-op-present-173991084 - My goal was to create replacement ASICs from the netlists.