It looks like there's a switch for whether VCC is provided by the hat or whether it assumes the target PCB is already providing power. I believe the ribbon cable is a 60 pin one so they might be using multiple lines for voltage.
For U2 you'd need the TSOP48 NAND adapter, their NOR one won't work. There are more adapters for the flashcat Mach/Xport here.Well, here to report my results with the clip, and not so good:
U2: Does not detect (using Parallel NAND mode).
U4: Detects correctly as AMD AM29LV160B using Parallel NOR mode, but does not read correctly. After 0x8000 offset, data is different from JTAG dump of U4. So only the first 0x8000 bytes are read correctly.
U23/U24: Does not detect using Parallel NOR mode.
I tried mashing down on the clip to get better contact, but same results. So unfortunately, it looks like it's not a viable solution, but if it did work, it would be able to read an entire NOR chip in a few seconds.
Unrelated, my version of Ibara appears to be different from the one in MAME - the CRC is different and at the boot screen the "BS" number is different. Not sure what "BS" stands for. The version screen still says 2005/03/22 MASTER VER..
MD5 hash of ibara-u4.bin: (from my PCB)
3d7ab67965c9ec58e67fd5ddcd84821f
MD5 hash of u4: (from the MAME set)
89f0a825ae32d3ef508d1603e96f0530
Hi, I did use the NAND adapter for that one, it still did not work. But I believe the problem is with the clip, as I tested it out with some memory chips not mounted on PCB and it exhibited the same problem with bad reads past 0x8000, which to me indicates that the address lines past that are not making good contact or are faulty on the clip. I'll have to take a look at the source code to see if I can resolve the undetected chips problem, but that might also be a clip related issue. I don't think it's a bus contention issue as I am halting the CPU before doing the read.For U2 you'd need the TSOP48 NAND adapter, their NOR one won't work. There are more adapters for the flashcat Mach/Xport here.
Also for the undetected NOR flash, you can use the source code for the flashcat software to add support yourself.
it's NAND, there is no address lines, but 8 data lines and 7 control lineswhich to me indicates that the address lines past that are not making good contact or are faulty on the clip
if you halt CPU does this change NAND control lines (iirc some of them connected to Altera CPLD, and at least one to SH3 GPIO port) ? I think no, it will retain last set stateI don't think it's a bus contention issue as I am halting the CPU before doing the read
Sorry if I wasn't clear - I meant the read was from NOR chip, not NAND. From what I understand NOR chips are similar to EPROMs with parallel address and data lines.if you halt CPU does this change NAND control lines (iirc some of them connected to Altera CPLD, and at least one to SH3 GPIO port) ? I think no, it will retain last set state
Sorry if I wasn't clear - I meant the read was from NOR chip, not NAND. From what I understand NOR chips are similar to EPROMs with parallel address and data lines.
For the CPU halt, I was grounding TRST on the JTAG interface, which from what I understand would halt all instructions including any activity from the Altera.
I see, sorry then.Sorry if I wasn't clear - I meant the read was from NOR chip, not NAND. From what I understand NOR chips are similar to EPROMs with parallel address and data lines.
For the CPU halt, I was grounding TRST on the JTAG interface, which from what I understand would halt all instructions including any activity from the Altera.