ATAPI/IDE ODE Testing

[rtw]

Older FPGAs always relied on uploading the bitstream to RAM in the FPGA device. Software would wait until the ready pin was asserted. My question is if the software checks if the ready pin is already asserted and if it is skips the upload ?

 

[uyjulian]

Older FPGAs always relied on uploading the bitstream to RAM in the FPGA device. Software would wait until the ready pin was asserted. My question is if the software checks if the ready pin is already asserted and if it is skips the upload ?

The only conditional checks in acfpgald before loading the bitstream are file related.

See
https://github.com/ps2dev/ps2sdk/bl...35df39896871/iop/arcade/acfpgald/src/fpgald.c

 

[rtw]

There seems to be some waiting for a given register status in the fpgald_wait function?