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ATAPI/IDE ODE Testing

Older FPGAs always relied on uploading the bitstream to RAM in the FPGA device. Software would wait until the ready pin was asserted. My question is if the software checks if the ready pin is already asserted and if it is skips the upload ?
 
There seems to be some waiting for a given register status in the fpgald_wait function?
 
I just got a preorder email for Tattiebogle IDE Simulator V3 and successfully placed an order. Hopefully orders will soon open up to people not on the waitlist.

Hi!

You are receiving this e-mail because you put your name on the list to be notified when the Tattiebogle ATAPI simulator was restocked.

The new V3 PCB is ready. This version has a new introductory price, lower than the original, though this price will likely increase going forwards due to the tariff situation.

Due to large demand, a pre-order system has been set up. If you're still interested, your details are as follows:

Maximum order quantity: 1
E-mail address: [redacted]
Preorder code: [redacted]

These details can be used at [redacted]

You can order less than the maximum, however the code will expire after a week even if not used.

Note that shipping to the UK is currently unavailable as we're still working on the VAT situation there.

Thanks!
Tattiebogle LLC
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