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gorgyrip

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I'm trying to make my own NEO-BUF using TSSOP20 because my eyes can't handle QFN anymore.

The story so far...
NEO-BUF has a 0.8mm pitch. I used square pads with a diameter of 0.6mm and a drill of 0.3mm.
The outline in the dimension layer is 0mil and it is positioned in the center of the hole.
In Eagle the board looks fine. But in other software the pads are almost gone.
I've attached a picture with the comparison.

What's the correct method for the outline for half vias/pads? If I move the outline 5mil on the outside, on some software the half pads looks decent.
Will JLCPCB do this board without selecting the "castellated holes" option? That will increase the price a lot...
 

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Other software might show your Gerber files differently, that might be related to the software rendering the Gerber and not your file. Also, if you input schematic/board to other software, it could change things a bit depending on the design rules, etc...

Castellated holes are a tricky thing to get right, and even if you pay extra for the option it's not a guaranteed yield that will be good, without burrs, via delamination, etc...

Make sure your design specs are how you want them and meet the fab houses' capabilities.

Each fab house has different capabilities of what they can do, jlcpcb are here:

https://jlcpcb.com/capabilities/Capabilities
 
How do you do it? You keep the dimension outline in the center of the hole?
 
How do you do it? You keep the dimension outline in the center of the hole?
Center, is almost mandatory for most fab places.

example
1627417621294.png

So after the holes are drilled, etc... the router bit then cuts through the middle o the hole so it might delaminate the plating material off the hole from one of the edges as it cuts through.

Some let you do a little less than half, etc... JLCPCB is low-cost enough for you to experiment with.

I would send out to make a board with a bunch of different size castellated pads/holes, etc.. the minimum order is 5 boards so you can see what happens when you get them made without selecting castellated service that way you can gauge what yield you can expect without issues.

Like the example above, its very tight and they can do it, but wont be exact, the router bit might eat a little bit more past your outline or maybe less, usually a little bit more. I would says before you commit to making a large run or final order to just order some test ones to see how they come out first.
 
I understand. It seems to be a lottery, especially for 0.3mm holes.
 
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I understand. It seems to be a lottery, especially for 0.3mm holes.
Yes and No, you can send out your pcb to be fabbed exactly as you designed with a few tolerances to certain pcb factories but it will just cost way more, don't think that's what you are looking for. Also, that design might be better on a flex pcb?
 
Yes, a flex pcb will be a lot better, but more expensive and it will not be worth it.
The design is just at the limit of the jlc specs for 2 layer pcb. If they will accept to do it without the castellated holes option the price will be 10$ for 100 pcs or 11$ for 200 pcs, plus 6-7$ for shipping. And plus VAT.
I will try my luck with an outline placed with 5mil on the outside from the center of the hole. Worst part, I will have to sand them a little. I've seen that GadgetUK has done that and he sanded a few millimeters.
But i will have to wait since our dear and beloved post and government just announced that everything from outside EU will arrive in customs.
 
Thank you!
I think i understand it now a little better:
1. no castellated holes: when the board is completed, the vias are cut in half.
2. castellated holes: after the cut, the holes are plated. (JLC calls it a special process)

What i don't understand about castellated holes on JLC:
The capabilities for via don't apply for castellated holes? Because I can't see the minimum annular ring on the castellated hole. That means that also the 0.5mm minimum clearence between holes from different nets doesn't apply anymore?
 

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