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Fluffy

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A quick test to convert the Verilog code for the PCM into discrete logic chips. I am not sure if I've got all inverters correct, you can probably use smaller latches, and I'm sure you could optimise out the counter... I'll have to double-check everything against the timing diagrams.
This is still going to take quite some space compared to a small CPLD.

The talk about the STM32 makes me think if you could run an OGG decoder on a microcontroller and then stream the result over an ADPCM channel to the NeoGeo. You'd ignore the address and just write to the data bus. Though probably only interesting for homebrew...
 

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stj

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i'v not seen that done, i'v seen playing WAV's, MP3's and SID files.
 

Hammy

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A quick test to convert the Verilog code for the PCM into discrete logic chips. I am not sure if I've got all inverters correct, you can probably use smaller latches, and I'm sure you could optimise out the counter... I'll have to double-check everything against the timing diagrams.
This is still going to take quite some space compared to a small CPLD.
https://www.mvs-scans.com/images/b/b6/Lansquenet_2004_bootleg1_b1_front.jpg

Looks about the same , plenty of 374's = looks like you have solved it the same.
With the hard one done the remains should be no problem :)
 

Fluffy

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If you want to use 27c322 you'll probably want to use 2x 74ls257 to convert the 16 bit bus into 8. I'd probably move the multiplex logic into a GAL to have some flexibility for debugging as well.

Not sure when I've got time to verify, route and test it... if anyone else wants to do it they're welcome.
 

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Quick draft of p-rom banking GALs. They rely on the bank address latched in a '273:
For 27c160:
Code:
PartNo Banking;
Date 18/01/2022;
Revision 01;
Designer Fluffy;
Company None;
Assembly None;
Location None;
Device g16v8;
Name banking_160;

/* Inputs */
Pin 1 = A20;
Pin 2 = A21;
Pin 3 = A22;
Pin 4 = A23;
Pin 5 = ROMOE;
Pin 6 = PORTOEL;
Pin 7 = PORTOEU;

/* Outputs */
Pin 19 = A20_I;
Pin 18 = A21_I;
Pin 17 = P1_CS;
Pin 16 = P2_CS;
Pin 15 = P3_CS;
Pin 14 = P4_CS;
Pin 13 = P_OE;

/* Logic */
A20_I = (!A20 & ROMOE);
A21_I = 'b'1;
P1_CS = (!A20 & A21 & ROMOE) # (A20 & !A22 & ROMOE) # (!A21 & A22 & ROMOE);
P2_CS = (A20 & A21) # !ROMOE # A22 # (!A20 & !A21);
P3_CS = (A20 & A22) # (!A21 & !A22) # !ROMOE # (!A20 & A21);
P4_CS = (A20 & A21) # !ROMOE # !A22 # (!A20 & !A21);
P_OE = (ROMOE & PORTOEL & PORTOEU);
For 27c322:
Code:
PartNo Banking;
Date 18/01/2022;
Revision 01;
Designer Fluffy;
Company None;
Assembly None;
Location None;
Device g16v8;
Name banking_322;

/* Inputs */
Pin 1 = A20;
Pin 2 = A21;
Pin 3 = A22;
Pin 4 = A23;
Pin 5 = ROMOE;
Pin 6 = PORTOEL;
Pin 7 = PORTOEU;

/* Outputs */
Pin 19 = A20_I;
Pin 18 = A21_I;
Pin 17 = P1_CS;
Pin 16 = P2_CS;
Pin 15 = P3_CS;
Pin 14 = P4_CS;
Pin 13 = P_OE;

/* Logic */
A20_I = (!A20 & ROMOE);
A21_I = (A20 & !A21 & ROMOE) # (!A20 & A21 & ROMOE);
P1_CS = (A20 & A21 & !A22 & ROMOE) # (!A20 & A23 & ROMOE) # (A22 & !A23 & ROMOE) # (!A21 & A23 & ROMOE);
P2_CS = (!A21 & !A22) # !ROMOE # (!A20 & !A22) # (A20 & A21 & A22) # A23;
P3_CS = (A20 & A21 & A23) # (!A20 & A22) # (!A21 & A22) # (!A22 & !A23) # !ROMOE;
P4_CS = (!A21 & !A22) # !ROMOE # !A23 # (!A20 & !A22) # (A20 & A21 & A22);
P_OE = (ROMOE & PORTOEL & PORTOEU);
Pinout may still change depending on routing requirements, and obviously untested.

It generates /OE for the roms based on ROMOE and PORTOE, accesses page 0 for ROMOE, and page (bank+1) for PORTOE.

(You could probably generate equations for various mixed '160 and '322 configurations if necessary - not that I can think of many use cases nowadays.)
 

Fluffy

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Yeah, 4x4MB P-ROM is overkill... but the space is there so why not? If you really need to cost-cut for a bigger production run you'll probably make a custom PCB anyway.
 

Fluffy

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This is going to be tight... though I guess I can move the EPROMs to make better use of the space.

MVS-Prog.jpg
 

Fluffy

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There are optional bits... You don't need to populate all EPROMs or the headers, and you don't need the '257 if you use 27c160 for audio.
I'll have to think if I can reduce the number of chips...
 

stj

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use 29f160 or bigger tsop flash - those are very easy to scavange. :)
 

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I think it's ideal like this, easy to get bits and much easier for development then soldering flash roms.
The jumpers could be swapped to solder pads (maybe the less important?) to save space....

Another thing would be some holes to join the 2pcb's together so a case is not required, but again this is something for at the end when there's a pair ;)
 

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This! the original design of using 0Ohm resistors is lame... no reason to not just have two pads next to each other than can accept a solder blob.
I assume they use 0ohm resistors so the boards can be configured during pick+place. At the moment I'm planning solder jumpers to bypass the '257 if you don't need the 16->8 conversion, and to configure wait states.
I'll need to have a closer look at the bootleg boards how they do V-ROM demultiplexing, and if they manage it with fewer chips.
 

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https://www.mvs-scans.com/images/b/b6/Lansquenet_2004_bootleg1_b1_front.jpg

Looks about the same , plenty of 374's = looks like you have solved it the same.
With the hard one done the remains should be no problem :)
Looking closely at the PCB it seems to work the same as the schematic (or Furrtek's Verlog). I think the '374 latch the addresses, while the SMD '373 to the left and on the bottom of the PCB latch the returned data. At the moment I'm not sure why the PCB uses '373 instead of '374, and why it uses the HC245 transceivers. Maybe it does 16->8 translation as well? Hard to tell, all the data lines are covered by chips...
 

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It's not much, but it is as much as I could trace visually:
Lansquenet_2004_bootleg1_b1.jpg


Questions:
- are the outputs of the HC245 (top and bottom) connected?
- are the inputs of the HC245 (top and bottom) connected to D0-D7 and/or D8-D15 of the EPROM?
- where are the pins of the LS161 counter connected? (Probably some of the OE and CLK of the LS374 or the inverter)
- where are the pins of the HC14 connected to?
- where are the OE and CLK of the '374 or '373 connected?
- where are the SDPOE, SDPMPX, SDROE and SDRMPX pins connected?

Signals will be connected to multiple chips, for example some CLK or OE pins of the some 374 will be connected together
I don't care about power connections, they'll be connected to GND/VCC.
You don't need to trace each and every data and address line - they'll most likely go onto similar locations.
Most important are the LS161 and the HC14.
No rush - do as much as you want when you have time.

Datasheets:
https://www.ti.com/lit/ds/symlink/sn74ls373.pdf
https://www.ti.com/lit/ds/symlink/sn74ls245.pdf
https://www.ti.com/lit/ds/symlink/sn74ls161a.pdf
https://www.ti.com/lit/ds/symlink/sn74ls14.pdf
https://wiki.neogeodev.org/index.php?title=MVS_cartridge_pinout
 
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