A quick test to convert the Verilog code for the PCM into discrete logic chips. I am not sure if I've got all inverters correct, you can probably use smaller latches, and I'm sure you could optimise out the counter... I'll have to double-check everything against the timing diagrams.
This is still going to take quite some space compared to a small CPLD.
The talk about the STM32 makes me think if you could run an OGG decoder on a microcontroller and then stream the result over an ADPCM channel to the NeoGeo. You'd ignore the address and just write to the data bus. Though probably only interesting for homebrew...
This is still going to take quite some space compared to a small CPLD.
The talk about the STM32 makes me think if you could run an OGG decoder on a microcontroller and then stream the result over an ADPCM channel to the NeoGeo. You'd ignore the address and just write to the data bus. Though probably only interesting for homebrew...