- Thread starter r67055
- Start date
YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).
| NEO-G0 | YM2610 |
| (2) | RAD0(17) |
| (3) | RAD1(16) |
| (4) | RAD2(15) |
| (5) | RAD3(14) |
| (15) | RAD4(13) |
| (16) | RAD5(12) |
| (17) | RAD6(11) |
(1 | RAD7(10) |
| NEO-G0 | PROG slot #1 |
| (6) | SDRAD0(B49) |
| (7) | SDRAD1(B50) |
| ( | SDRAD2(B51) |
| (9) | SDRAD3(B52) |
| (11) | SDRAD4(B53) |
| (12) | SDRAD5(B54) |
| (13) | SDRAD6(B55) |
| (14) | SDRAD7(B56) |
| NEO-G0 | PROG slot #2 |
| (62) | SDRAD0(B49) |
| (63) | SDRAD1(B50) |
| (64) | SDRAD2(B51) |
| (1) | SDRAD3(B52) |
| (21) | SDRAD4(B53) |
| (22) | SDRAD5(B54) |
| (23) | SDRAD6(B55) |
| (24) | SDRAD7(B56) |
Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.
| NEO-E0 | YM2610 |
| A7(16) | RA8(23) |
| A8(17) | RA9(22) |
| A9(1 | RA20(35) |
| A10(19) | RA21(36) |
| A11(20) | RA22(37) |
| A12(21) | RA23(3 |
| A13(31) | RMP 20) |
| A14(32) | /ROE(21) |
| NEO-E0 | PROG slot #1 & #2 |
| Y6(12) | SDRA8(A49) |
| Y7(13) | SDRA9(A50) |
| Y8(14) | SDRA20(A51) |
| Y9(22) | SDRA21(A52) |
| Y10(23) | SDRA22(A53) |
| Y11(24) | SDRA23(A54) |
| Y12(27) | SDRMPA55) |
| Y13(2 | SDROE(A56) |
| NEO-G0 | PROG slot #2 |
| (35) | SDPAD0(B41) |
| (36) | SDPAD1(B42) |
| (37) | SDPAD2(B43) |
| (3 | SDPAD3(B44) |
| (53) | SDPAD4(B45) |
| (54) | SDPAD5(B46) |
| (55) | SDPAD6(B47) |
| (56) | SDPAD7(B4 |
| I checked these lines. everything is OK |
I managed to fix the sound bug.YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).
NEO-G0 YM2610 (2) RAD0(17) (3) RAD1(16) (4) RAD2(15) (5) RAD3(14) (15) RAD4(13) (16) RAD5(12) (17) RAD6(11) (1 RAD7(10)
NEO-G0 PROG slot #1 (6) SDRAD0(B49) (7) SDRAD1(B50) ( SDRAD2(B51) (9) SDRAD3(B52) (11) SDRAD4(B53) (12) SDRAD5(B54) (13) SDRAD6(B55) (14) SDRAD7(B56)
NEO-G0 PROG slot #2 (62) SDRAD0(B49) (63) SDRAD1(B50) (64) SDRAD2(B51) (1) SDRAD3(B52) (21) SDRAD4(B53) (22) SDRAD5(B54) (23) SDRAD6(B55) (24) SDRAD7(B56)
Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.
NEO-E0 YM2610 A7(16) RA8(23) A8(17) RA9(22) A9(1 RA20(35) A10(19) RA21(36) A11(20) RA22(37) A12(21) RA23(3 A13(31) RMP A14(32) /ROE(21)
NEO-E0 PROG slot #1 & #2 Y6(12) SDRA8(A49) Y7(13) SDRA9(A50) Y8(14) SDRA20(A51) Y9(22) SDRA21(A52) Y10(23) SDRA22(A53) Y11(24) SDRA23(A54) Y12(27) SDRMP Y13(2 SDROE(A56)
NEO-G0 PROG slot #2 (35) SDPAD0(B41) (36) SDPAD1(B42) (37) SDPAD2(B43) (3 SDPAD3(B44) (53) SDPAD4(B45) (54) SDPAD5(B46) (55) SDPAD6(B47) (56) SDPAD7(B4 I checked these lines. everything is OK
both slots work fine.
NEO-G0 was at fault.
Thanks for the help!
I found a new type.
I don't know where to start.
Is it difficult to fix such a mistake?
View: https://youtu.be/vexIp2QfVo4
I don't know where to start.
Is it difficult to fix such a mistake?
Attachments
- Check the reset line of the CPU with a logic probe. When you power on the board you should expect it to start low and go high (it may end up pulsing because watchdog is resetting the board over and over)
- Use logic probe on pin 20 (output enable) of the bios chip, verify its pulsing
- Is there any obvious signs of damage (ie battery leakage) or re-work done on the board?
I tested it with a logic tester. high level is visible after switching on. it pulses with the same frequency as you can see in the video.
I checked the battery for leaks. There are no leaks on the pcb.
I saw damage to the NEO-G0, so I soldered it off.
NEO-G0 41pin shows damage. does not connect anywhere (41pin)
I did NOT put NEO-G0 back in the sheet. I turned on the board.
The watchdog image has stopped and "MAIN RAM TEST" is displayed.
I put another NEO-G0 back in the board. the watchdog is back.
Will the fault be on this line?
Attachments
Sounds like that NEO-G0 is getting enabled when it shouldn't be.
https://wiki.neogeodev.org/index.php?title=NEO-G0
If you look at the internal logic section it shows that pins 39 and 51 are what could enable parts of the program rom to pass to the CPU data bus. I would check to see what those pins are doing.
Also, In the lower left of the page it has the pinout for J4 on MV2B which should be the same as MV2F. In the comments for that it gives the impression those enable pins come from the NEO-I0 chip.
Your MAIN RAM TEST likely just means you have all your hard dips in the ON position. You also seem to have a 32K/slow vram related issue given the dupe/corrupt text.
https://wiki.neogeodev.org/index.php?title=NEO-G0
If you look at the internal logic section it shows that pins 39 and 51 are what could enable parts of the program rom to pass to the CPU data bus. I would check to see what those pins are doing.
Also, In the lower left of the page it has the pinout for J4 on MV2B which should be the same as MV2F. In the comments for that it gives the impression those enable pins come from the NEO-I0 chip.
Your MAIN RAM TEST likely just means you have all your hard dips in the ON position. You also seem to have a 32K/slow vram related issue given the dupe/corrupt text.
I followed the line between NEO-G0 pin 39-51 and NEO-I0. NEO-G0 pin 39 goes to NEO-I0 pin28.
NEO-G0 pin 51 goes to NEO-I0 pin27.
That's why I replaced the NEO-I0.
unibios 4.0 did not start. Black screen.
Original BIOS started.
The black screen on the unibios 4.0 is likely a bug. On some multi slot boards it will boot to the black screen if there are no cart(s) installed. Even if you have multiple of the same model number, one may always boot to black screen while the other to cross hatch. I've never been able to figure out the exact trigger.
I would try booting with the diag bios and see what it says. Something is going on with either your slow/32k vram or maybe accessing the sfix rom on the board. The wavy disappearing video in your video is likely a symptom of a broken trace somewhere. So you might just try logic probing your video ram / SFIX rom to see if any of the pins are dead.
began to probe with a logic probe.unfortunately, I can't find the DIAG ROM.(( I don't have the eprom erasing uv lamp here. I can write another one on Monday. I'll check the SFIXROM pins with a Logic probe.
I saw something strange in the SFIX rom 9 pin. when I touch the logic probe, the picture changes. SFIX pin9 connects to NEO-I0 pin 45.
Normally I would suggest trying to find that main tile/char being repeated over 90% of the screen in the sfix rom. This should be the empty/space tile (0x020), but as you can see its something else.
https://wiki.neogeodev.org/images/1/15/Fixref01.png
But I can't seem to find the tile on your screen in the sfix. You might try looking yourself, if you cant find it either I would suspect something with the sfix rom or the traces going to it.
https://wiki.neogeodev.org/images/1/15/Fixref01.png
But I can't seem to find the tile on your screen in the sfix. You might try looking yourself, if you cant find it either I would suspect something with the sfix rom or the traces going to it.
wow !!!! the NEO-I0 was bad. 1-2 slots same error screen. I look at the NEO-G0 lines.
