Resurrecting the 32/64MBIT flash project and 8/16 bit addressing.

Nice work.

It looks like you have the Q-15 dip pin connected to both 244s. I suspect you might run into issues when you are in 8bit mode. Specifically in that mode Q-15 from the dip will be an address signal coming from the MVS going to one of the LVC244s, but when the HCT244 that is also connected to that trace is enabled its going output a signal and cause a conflict. So I think you need another jumper that picks if the Q-15 dip is connect to the HCT244 or LVC244. I guess another possibility might be for the high byte HCT244 to never be enabled in 8 bit mode?
That issue was hitting me, when I thought it. You have read my mind. I'll try to figure it out
 
@ack Now the complete separation of Q15 signal is done.

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In resume:

J1 makes Chip Enable TSOP signal go to DIP42 PIN11

J2 makes A21 TSOP signal go to DIP42 PIN11
J3 makes Chip Enable TSOP signal go to GND

J8 and J6 make Q15 DIP42 signal go to LVC244 input/output order to Q15 TSOP
J4 make BYTE TSOP signal go to GND for 8bit mode

J9 and J7 make Q15 DIP42 signal go to HCT244 output/input order to Q15 TSOP
J5 make BYTE TSOP signal go to HIGH ( +3.3v ) for 16bit mode

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Bit late now but for the buffers wouldn't 74CBTD3384 be a better option? more pins so less chips needed and they seem to be more readily available. Maybe I'm missing something though as I haven't used either.
 
Bit late now but for the buffers wouldn't 74CBTD3384 be a better option? more pins so less chips needed and they seem to be more readily available. Maybe I'm missing something though as I haven't used either.
Hi. That chip is designed to play with signals that change direction everytime, so the 2 OE pins they have are an extra space.

Also those chips work with 10 input / outputs.

For input data pins you need max 22 signals + byte signal + Q15-A1 signal = 24. Using 3 chips make 6 signals not used.

For data bus direction you need 16 signals, so using 2 chips make 4 signals not used.

Not an appropiate option speaking in physical space concept, but thanks for suggesting it.
 
For 64mbit CAPCOM Sony ZN-2 eproms not, but for MVS / Sega Model 3 64mbit eproms yes
I'm curious to understand why these wouldn't work as replacements for EPROMS for games on ZN-2 - why wouldn't it work? Are the ICs different somehow on the ZN-2s?
 
PXL_20260223_190355283.jpg


Alright, that's my Shock Troopers 1 convert. It has a complete 8x32mbit graphic section and it works like a charm for now.

I have to test these boards with 64mbit roms with my Shock Troopers 2nd, because that game needs 32mbit (8bit) audio section and 8x64mbit (16 bit) on video section.

After that I'll pass the gerber to @ack for being sure this can be published for all people. I have to make the special 8MB P2 section for CPU, it works in my designs, but I have to convert it to level shifter system.
 
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Well, about the special CPU board for having 2x4MB P2 divided rom, I made in the past this working unit without 3.3V level shifter protection:

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It has been tested on my Samurai Shodown V Special, SNK VS Capcom Chaos and The King of Fighters 2003, all the decrypted roms.

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Well, it's designed now for that purpose. I have yet to test it, but it should world. I have to order them in the next batch in a month aprox.
 
PXL_20260223_190355283.jpg


Alright, that's my Shock Troopers 1 convert. It has a complete 8x32mbit graphic section and it works like a charm for now.

I have to test these boards with 64mbit roms with my Shock Troopers 2nd, because that game needs 32mbit (8bit) audio section and 8x64mbit (16 bit) on video section.

After that I'll pass the gerber to @ack for being sure this can be published for all people. I have to make the special 8MB P2 section for CPU, it works in my designs, but I have to convert it to level shifter system.
Can i ask you to start sharing C/V rom adapter ?
 
Is there any way to modify the pcb so the chip can be written onboard? Maybe some sort of optional header?
These would be far cheaper than 27c322.
 
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