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id rather buy a new cart and start all over again than doing that... and might even be faster, i guess 😅

Edit: has this ever been tested successfully with a V2 Cart?
If not I really might have to check continuity to the CPLDs, as the wiring might be different...
 
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Will definitely do so.
By the way: I was able to mess up my v3 cart by ripping some pins off...

Therefore I designed a new daughter/carrier PCB with THT 1.27 pins instead of SMD headers:
image-16.png

It's a 4-layer PCB and should be a drop-in replacement.

I even thought about creating a programmer board where you could simply remove the F0095H0 instead of the Daughter board...

Maybe next time 😅
Were you able to find anyone to manufacture it? I did something similar but adding support for a 2nd F0095H0 chip

Screenshot 2023-09-22 at 11.33.15 AM.png


However all the normal pcb manufactures want >0.6mm hole diameter and >0.6mm distance between holes for castellated holes. But the pitch needs to be 0.8mm, so I couldn't find anyone to make it.

I ended up just doing this (in production now), but not sure I will be able to solder the chips to it.

Screenshot 2023-09-26 at 8.41.38 AM.png
Screenshot 2023-09-26 at 8.42.26 AM.png
 
I just sent it to jlcpcb and there were no issues...
But I have to admit: I did not go for castellation but "cut vias".
Therefore there will be some rework necessary I guess... 😅

But I made such stuff in the past as well (even with lower pitch) and I never heard that the distance between castellated holes have to be .6mm for jlc. But maybe I just never read it 🤣
 
When I tried they rejected my order and sent this.

Screenshot 2023-09-26 at 9.00.03 AM.png


Can you give an example of what you did in your pcb layout?
 
Interesting 🤔
This goes against everything they write on their homepage 🤣

I can upload my kicad project if that's of any help.

And I just took the default settings for a 4 layer PCB.


Aaah! Now I see it: it is because you selected you wanted castellations. They have special rules for castellations... as I did not ask for them, the "regular rules" applied for my design
 

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Yeah I know.
Usually I just set the outline a little of center, so tolerances don't bother that much... forgot it this time 😅 but for prototypes and "at home stuff" it's usually good enough
 
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How are you envisioning the dual ROM working @ack ?
There are 2 daughterboards for the C roms allowing 2G of space. The idea would be to replace one of those daughterboard with this dual one to expand the space to 3G. The OE1/2 pads on the daughterboard get soldered to pins on the CPLD that are newly allocated for handling a 3rd C flash chip.

Having 3G of C rom space almost gets the full original set on the cart (no homebrew, no mahjong, no quiz, no stakes winner), the limitation becomes the available P rom space.
 
There are 2 daughterboards for the C roms allowing 2G of space. The idea would be to replace one of those daughterboard with this dual one to expand the space to 3G. The OE1/2 pads on the daughterboard get soldered to pins on the CPLD that are newly allocated for handling a 3rd C flash chip.

Having 3G of C rom space almost gets the full original set on the cart (no homebrew, no mahjong, no quiz, no stakes winner), the limitation becomes the available P rom space.
Love it, keep us updated with how it goes!
 
If you have something to fix or share and contribute to the project, please create a Pull Request in the git repo. (or here)
 
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Is it possible to add homebrew using VTXCart? I would love to add Neotris and Hypernoid
 
@ack could you confirm why 6 of the 2x22 1.27mm headers are required for the cart and 2x22 for the dumper board but no male headers are required?

Do you connect the cart to the dumper board with DuPont connectors?
 
Depending on the complexity of the CPLD design (number of games), the delay of some signals may increase.
Check the slacks in the Quartus timequest timing analyzer and add constraints to the .sdc files if necessary.
I checked the results and indeed: the slack for PCK1B, SDRD0 and PCK2B is -3.500 and afaik this means the design is "not runnable".

Unfortunately i'm still a newbie in the CPLD/FPGA stuff and have very basic knowledge... i can create vhdl code but that's it...
If its not too complicated could you tell me, what i need to do?

Edit: I found a constrains file in one of the projects generating a 50mhz clock with period 20.

Would this be the same requirements for the other clocks?
 
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If you have something to fix or share and contribute to the project, please create a Pull Request in the git repo. (or here)
I will. I have the compiler and (mvs) cpld changes made, but holding off on submitting until I'm able to test them.
 
@ack could you confirm why 6 of the 2x22 1.27mm headers are required for the cart and 2x22 for the dumper board but no male headers are required?

Do you connect the cart to the dumper board with DuPont connectors?

IMG_1047.jpg


The C and V flash chips come on daughterboards (top left board). They have a 2 male 2x22 1.27mm connectors that are soldered directly to the cart. The 6x female connectors for the cart aren't required, but it makes the daughterboards plugable. On the cart board above I installed the female connectors on the right location but not the left one yet. Additionally the 2x22 1.27mm female connectors are require on the dumper board because of hole alignment issues.
 
I thought that might be the case but wanted to confirm. I ordered both male and female 1.27mm headers just in case
 
IMG_1047.jpg


The C and V flash chips come on daughterboards (top left board). They have a 2 male 2x22 1.27mm connectors that are soldered directly to the cart. The 6x female connectors for the cart aren't required, but it makes the daughterboards plugable. On the cart board above I installed the female connectors on the right location but not the left one yet. Additionally the 2x22 1.27mm female connectors are require on the dumper board because of hole alignment issues.
Nice work!! Can you close the cart with the connectors in place?
 
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